Reconfigurable scan networks: formal verification, access optimization, and protection

clock .. . . . primary data/control inputs .. parallel scan data input primary data outputs Figure 4.7.: CSU-accurate FSM representation of a reconfigurable scan network a full CSU operation, i.e., multiple clock cycles in the cycle-accurate RSN model. An example is given in Figure 4.6 where k cycles of a CSU operation are combined into a single transition in the CAM. The block diagram of a CSU-accurate FSM is depicted in Figure 4.7. Compared with the cycle-accurate FSM model from Figure 4.5, the CSU-accurate FSM has no inputs that control the three phases of a CSU operation, and neither a scan-input nor a scanoutput. Instead of representing the scan data as a sequence of bits at the scan-input, the scan data of a CSU operation are modeled as a bit vector. Scan data for each scan segment are provided to the CSU-accurate FSM via the parallel scan data input. In each state transition (cycle of the abstract clock that models a CSU operation), the parallel scan data are transferred to the corresponding scan segment if and only if this scan segment is selected and belongs to the active scan path.